1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly relates to a structure of a MONOS memory cell, e.g., it is applicable to a NAND type and a NOR type of flash memory.
2. Description of the Related Art
EEPROM has been developed which is provided with an array of electrically programmable and erasable memory cells and which is one of non-volatile semiconductor memory devices. The EEPROM is one in which information of digital bits are read by measuring a change in conductance of a transistor according to the amount of charge injected into a charge accumulation layer by a tunneling current from a channel of a cell transistor through an insulating film. In the EEPROM, there are a MONOS memory, a MNOS memory, and a memory having a floating gate structure.
The MONOS memory uses a cell transistor having a structure of metal/oxide film/nitride film/oxide film/semiconductor region. When a SiN film is used as the charge accumulation layer of the cell transistor, low-voltage programming or low-voltage erasing operation can be performed, compared with a memory using a polysilicon floating gate. One example of a structure of the cell transistor and a manufacturing process of such MONOS memory is disclosed in Japanese Patent Laid-Open 284627/1998.
FIGS. 10A and 10B show one example of a gate sectional structure which includes the cell transistor of a memory cell region and a MISFET of a peripheral circuit region in the manufacturing process of the conventional MONOS memory.
In FIGS. 10A and 10B, a stacked gate of the cell transistor has the structure in which a first silicon oxide film 24, a silicon nitride film (charge accumulation layer) 25, a second silicon oxide film 26, and a gate electrode 28 of polysilicon are stacked in order on a semiconductor substrate 21. The first silicon oxide film 24 has a function of intentionally passing through the charges, and the second silicon oxide film 26 has the function of blocking current between the silicon nitride film 25 and the gate electrode 28.
On the other hand, in the MISFET, the gate electrode 28 is formed on the semiconductor substrate 21 through a gate insulating film 22. A gate sidewall film 23 of PSG is formed as gate sidewall spacers of these cell transistors and the MISFET.
In the semiconductor substrate 21, a source region and a drain region (hereinafter referred to as source/drain region) 29 of the cell transistor are provided, and the source/drain region 29′ of the MISFET is provided.
One example of a method forming the cell transistor is described in the above-described patent document.
That is, as shown in FIG. 10A, when the gate electrode 28 of the cell transistor is etched, the polysilicon film is etched down to the first silicon oxide film 24 so that the gate electrode 28 is formed in a desired shape.
Then, for example, phosphorus is ion-implanted with a dose of 1.5×1013 cm−2, as shown in FIG. 10B, thereby providing an n-type region having a low concentration, which becomes part of the source/drain region 29.
Thereafter, the insulating film of PSG is deposited, and the gate sidewall film 23 is left in the gate sidewall. Further, phosphorus is ion-implanted with a condition of 5×1015 cm−2 to provide the n-type region having a high concentration which becomes part of the source/drain region 29.
The n-type region of the low concentration is formed in the source/drain region 29 in order to prevent drain breakdown voltage at a gate edge from decreasing.
When the MISFET of the peripheral circuit is formed on the same substrate as the cell transistor by using the same gate electrode material, in the related art, gate electrode processes are performed simultaneously for reducing the process. This results in a problem of reliability of the MISFET. The problem will be described bellow.
As shown in FIG. 10A, when the polysilicon film of the gate electrode 28 in the MISFET is etched through the gate insulating film (thermal oxidation film) 22 formed on the semiconductor substrate 21, a selection ratio of the etching of the gate electrode 28 to the gate insulating film 22 is not infinite. Therefore, a film thickness of the gate insulating film 22 is decreased in etching the gate electrode 28, undercut will be slightly generated under the gate electrode 28.
Then, as shown in FIG. 10B, after the n-type region of the low concentration is formed, which becomes part of the source/drain region 29′, the PSG film is deposited and etched to form the gate sidewall film 23 of the cell transistor. In this case, the gate sidewall film 23 is also formed in a gate edge portion of the MISFET.
Generally, the deposited silicon oxide film including the PSG film deposited on the gate sidewall film 23 has less breakdown voltage characteristics, compared with the gate insulating film 22 formed by the thermal oxidation of the silicon substrate, so that the breakdown voltage of the gate insulating film between the source/drain region 29′ and the gate electrode 28 is degraded and a leakage current is increased.
Further, the above-described patent document describes that after the n-type region of the high concentration which becomes part of the source/drain regions 29 and 29′ is produced, an interlayer insulating film made of BPSG or PSG is deposited and the silicon nitride film is formed on the memory cell by a plasma chemical vapor deposition method.
However, a large amount of hydrogen, which is generated in forming the silicon nitride film or contained in the silicon nitride film, is easily diffused into silicate glass such as PSG and BPSG during, e.g., an after-thermal process such as a sintering process. As a result, the hydrogen changes trap density of SiN, which becomes the charge accumulation layer 25, and surface state density of the tunneling insulating film, and charge retaining characteristics of the cell transistor are fluctuated by depositing conditions of SiN or presence or absence of the deposition, which causes the reliability to be decreased.
Also, the above-described patent document describes that BPSG or PSG is used as the interlayer insulating film and heat treatment for viscous flow is performed under conditions of 900° C. for 30 minutes.
However, in the heat treatment, moisture or hydronium ion which is contained in BPSG or PSG is diffused to oxidize the gate edge, so that a shape of the gate edge is changed.
Similarly to the above-described explanation, when inorganic glass made of, e.g., cyclopentasilane or polysilazane is used as the interlayer insulating film, an oxidation process is required for transformation into the inorganic glass, the gate edge is oxidized by the thermal process and the shape of the gate edge is changed.
As described above, in the structure of the cell transistor of the MONOS memory, when the MISFET is formed on the same substrate by using the same gate electrode material, the reliability of the gate insulating film in the MISFET is decreased, and further when the oxidation process is introduced for transformation into the inorganic glass which becomes the interlayer film, the moisture in the silicate glass which becomes the interlayer insulating film oxidizes the gate edge, and the shape of the gate edge portion is changed to decrease the reliability.
Further, it has been uncertain what sidewall shape of the gate electrode in the cell transistor of the MONOS memory can suppress worsening of the characteristics, which is caused by short channel effect in a gate length, e.g., not more than 0.2 μm, of the cell transistor, and/or improve erasing speed.